Free RAM latency calculator: turn CAS latency and MT/s into nanoseconds, compare your kit against the JEDEC speed bin, and price tRCD and tRP.
The data rate is the number in the module name, in MT/s — DDR5 is published from 3,200 to 8,800. If a tool reports MHz, double it: the clock runs at half the data rate.
The fastest bin JEDEC publishes at each DDR5 data rate, with the latency it works out to. A module boots at one of these until an XMP or EXPO profile is enabled.
Transcribed from Micron's speed-bin tables, which list clock frequency and data rate separately.
| Speed bin | Module | Clock | CL | Latency |
|---|---|---|---|---|
| DDR5-3200 | PC5-3200 | 1,600 MHz | CL 26 | 16.25 ns |
| DDR5-3600 | PC5-3600 | 1,800 MHz | CL 30 | 16.67 ns |
| DDR5-4000 | PC5-4000 | 2,000 MHz | CL 32 | 16 ns |
| DDR5-4400 | PC5-4400 | 2,200 MHz | CL 36 | 16.36 ns |
| DDR5-4800 | PC5-4800 | 2,400 MHz | CL 40 | 16.67 ns |
| DDR5-5200 | PC5-5200 | 2,600 MHz | CL 42 | 16.15 ns |
| DDR5-5600 | PC5-5600 | 2,800 MHz | CL 46 | 16.43 ns |
| DDR5-6000 | PC5-6000 | 3,000 MHz | CL 48 | 16 ns |
| DDR5-6400 | PC5-6400 | 3,200 MHz | CL 52 | 16.25 ns |
| DDR5-6800 | PC5-6800 | 3,400 MHz | CL 56 | 16.47 ns |
| DDR5-7200 | PC5-7200 | 3,600 MHz | CL 58 | 16.11 ns |
| DDR5-7600 | PC5-7600 | 3,800 MHz | CL 62 | 16.32 ns |
| DDR5-8000 | PC5-8000 | 4,000 MHz | CL 64 | 16 ns |
| DDR5-8800 | PC5-8800 | 4,400 MHz | CL 72 | 16.36 ns |
Latency here is the memory device's own timing. What a program waits for also includes the controller, the interconnect and queueing on a loaded system, so measured latency is always higher than the figure a timing set implies.
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A kit labelled DDR5-6000 CL30 tells you two numbers and neither one is time. This calculator turns them into nanoseconds, then puts the answer next to the JEDEC speed bin published for the same data rate — so you can see whether a kit is genuinely quicker than the standard or just carrying a bigger number on the box.
CAS latency (CL, or tAA in the specification) is how many clock cycles pass between the memory controller asking for a column of data and that data arriving. It is counted in cycles, not in time, which is why CL alone tells you nothing: a cycle on DDR4-2400 lasts 0.833 ns and a cycle on DDR5-6000 lasts 0.333 ns. Multiply CL by the cycle time and you get true latency in nanoseconds, the only figure that compares two kits fairly. That is also why DDR5 kits carry much larger CL numbers than DDR4 while landing in the same place: the cycles got shorter, so it takes more of them to cover the same nanoseconds.
True latency
10.00 ns, and the JEDEC DDR5-6000 bin is CL48 at 16.00 ns — 37.5% faster than the standard.
16.67 ns. This is the JEDEC DDR5-4800 bin itself, so it matches the standard exactly.
8.89 ns. No JEDEC bin runs DDR4 that fast, so it is compared against DDR4-3200: 35.4% faster.
14.17 ns, against 13.33 ns for the CL16 bin at the same rate — 6.3% slower than the standard.
DDR5-6000 CL30 and DDR4-3200 CL16 both land on 10.00 ns. The CL numbers differ by 14 and the kits are equally quick to first data.
Every JEDEC speed bin from DDR2-400 to DDR5-8800 sits between 11 and 17 ns. Thirty years of higher data rates bought bandwidth, not latency — which is why comparing a kit against its own bin is more useful than comparing it against a grade.
CL is what a read costs when the row is already open. Enter tRCD and tRP and you can see what the same read costs when it is not, which is where slow memory actually hurts.
Data rate sets bandwidth; CL and the data rate together set latency. A faster kit with a proportionally larger CL gives you more of the first and none of the second.
Lower CL is better only at the same data rate. Across data rates it means nothing on its own: CL40 at 4800 MT/s is 16.67 ns and CL48 at 6000 MT/s is 16.00 ns, so the larger CL is the quicker kit. Convert both to nanoseconds before you compare.
MT/s. A DDR module transfers on both edges of its clock, so DDR4-3200 runs a 1600 MHz clock and moves 3200 megatransfers per second. Memory vendors and JEDEC label modules by the data rate; tools that report a clock show half the number. Micron's speed-bin tables list clock frequency and data rate as two separate columns for this reason.
They answer different questions. The data rate sets bandwidth, which matters for work that streams memory: video encoding, compression, large compiles, integrated graphics. True latency in nanoseconds matters for work that chases pointers, which includes most game engines. A kit that raises the data rate and CL together buys bandwidth and leaves latency where it was.
They are the other three numbers in a rating like 30-38-38-96. tRCD is the delay from opening a row to reading a column, tRP is the time to close a row before another can open, and tRAS is how long a row must stay open. CL alone applies when the row you want is already open; tRCD is added when it is closed, and tRP as well when the wrong row is open. This calculator shows all three cases once you enter them.
Because the published CL rises in step with the data rate. DDR5-3200 is CL26 and DDR5-8800 is CL72, and both work out near 16 ns. Improvements in DRAM have gone into bandwidth and density rather than access time, so the specification's guaranteed latency has barely moved in two decades. Kits faster than that exist — they are binned parts sold above the standard, which is what XMP and EXPO profiles configure.
Yes, and that is the point of them. Without a profile enabled a module boots at a JEDEC bin, which is the slower row in this page's table. XMP (Intel) and EXPO (AMD) load the data rate and the timings the kit was sold with. Enter the advertised figures to see what the profile is buying you.
No. Latency is CL multiplied by the cycle time in every generation, and a 64-bit module moves 8 bytes per transfer in every generation. What the generation does decide here is which speed bins your kit is measured against and whether the data rate you entered is one the standard publishes at all — DDR2, for example, ends at DDR2-1066.